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Difference between revisions of "Schematic:CPU, Memory, and Main Memory Decoder"

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Image:memdec.png|800px|alt=CPU, Memory, and Main Memory Decoder Circuit|Image map example. Clicking on a person in the picture causes the browser to load the appropriate article.
 
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Revision as of 19:25, 12 March 2011

Here is my WIP memory decoder showing flash ICs and one SRAM. There will be a total of 6 SRAMS for a total of 12MB RAM. SRAM0-SRAM5 will be wired exactly the same way execpt different MDCE pins (MDCE2-MDCE7).

Pasqual Paoli - Corsican patriotCPU, Memory, and Main Memory Decoder Circuit
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