Hardware:Schematic Busses

In the schemtics, you will see several busses & signal lines. They are described here:

Busses

System Busses
Name	Description
ADDR	Address Bus (Numbered as per CPU A1-A23)
DATA	Data Bus (D0-D15)
MDCE	Main Decoder Chip Enable/Select (MDCE0-MDCE7). These are the outputs from the main 74LS138 (See Memory Map)
IDCE	I/O Device Chip Enable/Select (IDCE0-IDCE7 or IDCE15). These are the outputs from the second 74LS138 or 74LS154 (See Memory Map)
IRQ	8 IRQ lines from the MFP for use by peripherals.)

Signals

For simplicity's sake when I say "device" in reference to memory/IO functions I mean the memory chip or I/O device.
Name's prefixed with / mean they are active low signals.

Signals
Short Name	Long Name	Description
/AS	Address Strobe	Asserted by bus master when accessing memory space, used as a chip enable for selected address.
/DTACK	Data Transfer Acknowledge	Read operation: asserted by device when it has output valid data onto the data bus. Write operation: asserted when data write is complete. Note: Any outputs to this line must be done with open-collector outputs!
/IACK	Interrupt Acknowledge	Low during an interrupt acknowledge when FC0-2 are all high. High during other CPU states.
/UDS	Upper Data Strobe	Asserted by bus master when reading/writing an upper (even) byte in address space (whether 8 or 16-bit transfer is taking place).
/LDS	Lower Data Strobe	Asserted by bus master when reading/writing an lower (odd) byte in address space (whether 8 or 16-bit transfer is taking place).
R/W	Read/Write	Asserted by bus master when reading/writing, HIGH = Read, LOW = Write
/RD	Read	Convenience signal decoded from R/W, will always be high or low and never tri-state unlike R/W.
/WR	Write	Convenience signal decoded from R/W, will always be high or low and never tri-state unlike R/W.
/WR_UDS	Write (Upper Byte)	Convenience signal for 8-bit devices for Write Enable when an upper (even) byte needs to be read or written.
/WR_LDS	Write (Lower Byte)	Convenience signal for 8-bit devices for Write Enable when an lower (odd) byte needs to be read or written.
/RESET	Reset	Held low to reset CPU & all devices. Can be held low by CPU or other device such as watchdog IC.