Hardware:Schematic Busses

In the schemtics, you will see several busses. They are described here:

Busses
Name	Description
ADDR	Address Bus (Numbered as per CPU A1-A23)
DATA	Data Bus (D0-D15)
MDCE	Main Decoder Chip Enable/Select (MDCE0-MDCE7). These are the outputs from the main 74LS138 (See Memory Map)