Difference between revisions of "Hardware:Schematic Busses"
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Revision as of 15:02, 9 March 2011
In the schemtics, you will see several busses. They are described here:
| Busses | |
|---|---|
| Name | Description |
| ADDR | Address Bus (Numbered as per CPU A1-A23) |
| DATA | Data Bus (D0-D15) |
| MDCE | Main Decoder Chip Select (MDCE0-MDCE7). These are the outputs from the main 74LS138 (See Memory Map) |
