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Difference between revisions of "Schematic:CPU, Memory, and Main Memory Decoder"

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(Created page with "Here is my WIP memory decoder showing flash ICs and one SRAM. There will be a total of 6 SRAMS for a total of 12MB RAM. SRAM0-SRAM5 will be wired exactly the same way execpt diff...")
 
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Revision as of 18:30, 11 March 2011

Here is my WIP memory decoder showing flash ICs and one SRAM. There will be a total of 6 SRAMS for a total of 12MB RAM. SRAM0-SRAM5 will be wired exactly the same way execpt different MDCE pins (MDCE2-MDCE7).

Memdec.png

Pasqual Paoli - Corsican patriotCPU, Memory, and Main Memory Decoder Circuit
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