User contributions
From Motorola 68000 Homebrew Computer Project
- 23:44, 3 March 2020 diff hist -106 Hardware:Memory Map current
- 03:29, 21 March 2011 diff hist +352 Software:OS current
- 18:00, 16 March 2011 diff hist 0 N File:Eurofemale.jpg current
- 18:00, 16 March 2011 diff hist 0 File:Euromale.jpg uploaded a new version of "File:Euromale.jpg" current
- 17:59, 16 March 2011 diff hist 0 N File:Euromale.jpg
- 17:58, 16 March 2011 diff hist +126 Hardware:Expansion Bus current
- 17:57, 16 March 2011 diff hist +291 N Hardware:Expansion Bus Created page with "Currently I am planning on using Eurocard (DIN 41612) connections for the backplane for the main board and expansion boards. {| border="1" !colspan="2"|Eurocard Connector |- |al..."
- 17:53, 16 March 2011 diff hist +6 Main Page →Individual Components current
- 17:53, 16 March 2011 diff hist +41 Main Page →Individual Components
- 04:45, 14 March 2011 diff hist 0 File:Mfp.png uploaded a new version of "File:Mfp.png" current
- 04:44, 14 March 2011 diff hist 0 MediaWiki:Licenses current
- 04:43, 14 March 2011 diff hist +1,322 N MediaWiki:Licenses Created page with "* Creative Commons licenses ** cc-by-sa-nc-3.0|Attribution ShareAlike NonCommercial 3.0 ** cc-by-sa-3.0|Attribution ShareAlike 3.0 ** cc-by-sa-2.5|Attribution ShareAlike 2.5 ** c..."
- 04:31, 14 March 2011 diff hist 0 N File:Mfp.png
- 04:30, 14 March 2011 diff hist -165 Schematic:MFP current
- 04:29, 14 March 2011 diff hist +269 N Schematic:MFP Created page with "Here is my WIP memory decoder showing flash ICs and one SRAM. There will be a total of 6 SRAMS for a total of 12MB RAM. SRAM0-SRAM5 will be wired exactly the same way execpt diff..."
- 04:27, 14 March 2011 diff hist 0 File:Memdec.png uploaded a new version of "File:Memdec.png" current
- 04:26, 14 March 2011 diff hist +56 Main Page →Schematics
- 04:24, 14 March 2011 diff hist -16 Hardware:Schematic Busses →Signals current
- 04:24, 14 March 2011 diff hist -1 Hardware:Schematic Busses →Signals
- 04:23, 14 March 2011 diff hist +199 Hardware:Schematic Busses
- 15:33, 12 March 2011 diff hist -41 Hardware:CPU current
- 15:32, 12 March 2011 diff hist 0 Schematic:CPU, Memory, and Main Memory Decoder current
- 15:31, 12 March 2011 diff hist +131 Schematic:CPU, Memory, and Main Memory Decoder
- 15:25, 12 March 2011 diff hist +6 Schematic:CPU, Memory, and Main Memory Decoder
- 22:26, 11 March 2011 diff hist -28 Schematic:CPU, Memory, and Main Memory Decoder
- 18:30, 11 March 2011 diff hist +278 Schematic:CPU, Memory, and Main Memory Decoder
- 03:01, 11 March 2011 diff hist 0 Schematic:Reset Circuit current
- 03:01, 11 March 2011 diff hist 0 N File:Reset.gif current
- 03:00, 11 March 2011 diff hist +170 N Schematic:Reset Circuit Created page with "This schematic was found on the internet but I don't really see a reason to change it. I may use a MAX283 instead though since it has watchdog input. Image:reset.gif"
- 03:00, 11 March 2011 diff hist +55 Main Page →Schematics
- 02:52, 11 March 2011 diff hist 0 File:Memdec.png uploaded a new version of "File:Memdec.png"
- 02:50, 11 March 2011 diff hist +11 Main Page →Memory Map & Busses
- 02:47, 11 March 2011 diff hist +1,886 Hardware:Schematic Busses
- 02:22, 11 March 2011 diff hist +1,225 Hardware:Memory Map
- 02:01, 11 March 2011 diff hist +236 N Schematic:CPU, Memory, and Main Memory Decoder Created page with "Here is my WIP memory decoder showing flash ICs and one SRAM. There will be a total of 6 SRAMS for a total of 12MB RAM. SRAM0-SRAM5 will be wired exactly the same way execpt diff..."
- 02:00, 11 March 2011 diff hist +152 Main Page
- 01:55, 11 March 2011 diff hist -2 Main Page →History of the Project
- 01:55, 11 March 2011 diff hist +59 Main Page
- 03:47, 10 March 2011 diff hist +6 Hardware:Memory Map
- 03:46, 10 March 2011 diff hist 0 File:Memdec.png uploaded a new version of "File:Memdec.png"
- 03:44, 10 March 2011 diff hist 0 File:Memdec.png uploaded a new version of "File:Memdec.png"
- 03:41, 10 March 2011 diff hist +6 Hardware:Memory Map
- 03:40, 10 March 2011 diff hist +65 Hardware:Memory Map
- 03:19, 10 March 2011 diff hist 0 File:Memdec.png uploaded a new version of "File:Memdec.png"
- 01:43, 10 March 2011 diff hist 0 N File:SST39SF040.pdf current
- 01:41, 10 March 2011 diff hist +50 Hardware:ROM current
- 23:47, 9 March 2011 diff hist +1 Main Page
- 23:44, 9 March 2011 diff hist 0 File:ZeDOS-logo.png uploaded a new version of "File:ZeDOS-logo.png" current
- 21:16, 9 March 2011 diff hist 0 File:ZeDOS-logo.png uploaded a new version of "File:ZeDOS-logo.png"
- 21:04, 9 March 2011 diff hist 0 N File:ZeDOS-logo.png
- 21:04, 9 March 2011 diff hist +39 Software:OS
- 20:21, 9 March 2011 diff hist +648 N Software:OS Created page with "I plan on writing a basic operating system called ZeDOS for the computer. The name ZeDOS comes from the OS I made for my old Z80 system and the 68000 will be ported and expanded ..."
- 20:03, 9 March 2011 diff hist 0 N File:68440.pdf current
- 20:01, 9 March 2011 diff hist +69 Hardware:Other ICs current
- 19:39, 9 March 2011 diff hist -1 Software:libc current
- 19:39, 9 March 2011 diff hist +4 Software:libc
- 19:39, 9 March 2011 diff hist +3 Software:libc
- 19:38, 9 March 2011 diff hist +721 N Software:libc Created page with "We'll be needing a libc and I've rounded up a few candidates. libc will be statically linked initially until shared libraries are implemented; that is something to keep in mind a..."
- 19:22, 9 March 2011 diff hist +43 Main Page →Software
- 15:04, 9 March 2011 diff hist +7 Hardware:Schematic Busses
- 15:03, 9 March 2011 diff hist +7 Hardware:Schematic Busses
- 15:02, 9 March 2011 diff hist +390 N Hardware:Schematic Busses Created page with "In the schemtics, you will see several busses. They are described here: {| border="1" !colspan="2"|Busses |- !Name||Description |- |align="center"|ADDR||Address Bus (Numbered as..."
- 14:58, 9 March 2011 diff hist +43 Main Page →Hardware
- 04:56, 9 March 2011 diff hist +42 N File:Memdec.png Work in progress memory circuit. 3/9/2011.
- 04:55, 9 March 2011 diff hist +226 Hardware:Memory Map
- 04:48, 9 March 2011 diff hist +497 N Hardware:Memory Map Created page with "The 16MB of address space will be broken up into 8 2MB chunks by a 74LS138 3-to-8 decoder. 0MB: 0x00000000 - 0x000FFFFF ROM 1 MB 1MB: 0x00100000 - 0x001FFFFF Reserved 1 MB, po..."
- 04:42, 9 March 2011 diff hist +252 N Hardware:RAM Created page with "RAM will be made up of 6 1Mx16-bit (2MB) SRAM chips. This is one of my few departures into SMT territory as these will be TSOP-1 48-pin ICs. Sorry, but DIP/PLCC SRAM is waaay to..." current
- 04:39, 9 March 2011 diff hist +162 N Hardware:ROM Created page with "1MB of ROM will be provided by 2 512x8-bit FLASH chips interleaved even/odd with the UDS/LDS signals from the CPU. Flash chips will be: SST39SF040 or compatible."
- 04:35, 9 March 2011 diff hist 0 N File:68901.pdf current
- 04:34, 9 March 2011 diff hist 0 N File:68681.pdf current
- 04:34, 9 March 2011 diff hist +6 Hardware:Other ICs
- 04:34, 9 March 2011 diff hist +204 N Hardware:Other ICs Created page with "68681 DUART (Dual UART + 8-bit GPIO) Datasheet 68901 Multi-Function Peripheral (MFP) (16 source interrupt controller, 1x UART/USRT, 4x timers, 8-bit GPIO) [[M..."
- 04:21, 9 March 2011 diff hist +43 Main Page →Hardware
- 03:56, 9 March 2011 diff hist +40 Hardware:CPU
- 03:55, 9 March 2011 diff hist +29 File:68000.jpg current
- 03:55, 9 March 2011 diff hist +35 File:68000.jpg
- 03:54, 9 March 2011 diff hist +7 Hardware:CPU
- 03:52, 9 March 2011 diff hist 0 N File:68000.jpg
- 03:51, 9 March 2011 diff hist +24 Hardware:CPU
- 03:51, 9 March 2011 diff hist +22 Hardware:CPU
- 03:48, 9 March 2011 diff hist +2 Hardware:CPU →References
- 03:45, 9 March 2011 diff hist 0 Hardware:CPU
- 03:44, 9 March 2011 diff hist 0 N File:M68KPROGMAN.PDF current
- 03:43, 9 March 2011 diff hist 0 N File:TS68C000 Datasheet.pdf current
- 03:42, 9 March 2011 diff hist +63 Hardware:CPU
- 03:31, 9 March 2011 diff hist +513 Hardware:CPU
- 03:08, 9 March 2011 diff hist +7 Hardware:CPU
- 03:07, 9 March 2011 diff hist +300 N Hardware:CPU Created page with "The Motorola 68000 CPU was released in 1979. It has a 32-bit instruction set and registers, with a 24-bit address bus and 16-bit data bus. More general information on this proces..."
- 03:02, 9 March 2011 diff hist +2 Main Page
- 03:01, 9 March 2011 diff hist 0 Main Page
- 01:15, 9 March 2011 diff hist +529 Main Page
- 01:07, 9 March 2011 diff hist +241 Main Page
- 01:03, 9 March 2011 diff hist +1,080 Main Page
- 00:48, 9 March 2011 diff hist -115 Main Page